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UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION Rev. 0.9 Rev. 1.0 DESCRIPTION Original. Revised - The test condition of ICC1 and ICC2 - Symbols CE#,OE# and WE# CE , OE and WE - The ordering information of package ,STSOP-1 is revised as STSOP. Revised - Improve IDR from 20A to 10A (LL-version , max.) - Package outline dimension Revised - Add Standby Current ISB1=20A for special requirement ( LL-version , max. ) - Ordering information in Standby Current column ( maximum typical ) - Standby Current in FEATURES section Rev.1.1 : 3mA (typical) normal Rev.1.2 : 0.3mA (typical) normal - Cycle time condition of ICC2 in DC electrical characteristics Rev.1.1 : Tcycle=1ms Rev. 1.2 : Tcycle=1s - Waveforms - Add under/overshoot range of VIL & VIH Add order information for lead free product DATE Apr. 26,2001 May. 14,2001
Rev. 1.1
May 14,2002
Rev. 1.2
May 20,2002
Rev. 1.3
May 15,2003
____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62256C is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT62256C is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT62256C operates from a single 5V power supply and all inputs and outputs are fully TTL compatible
FEATURES
Access time : 35/70ns (max.) Low power consumption: Operating : 40/30 mA (typical.) Standby : 0.3mA (typical) normal 2uA (typical) L-version 1uA (typical) LL-version Single 5V power supply All inputs and outputs are TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
A14 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
32K N 8 MEMORY ARRAY
A7 A6 A5 A4 A3 A2 A1
A13 A8 A9 A11
OE
A0-A14
DECODER
UT62256C
Vcc Vss
A10
CE
I/O1-I/O8
I/O DATA CIRCUIT
COLUMN I/O
A0 I/O1 I/O2 I/O3 Vss
I/O8 I/O7 I/O6 I/O5 I/O4
CE WE CONTROL CIRCUIT
OE
A11 A9 A8 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PDIP/SOP
28 27 26 25 24 23 22 A10
OE
CE
I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
PIN DESCRIPTION
SYMBOL A0 - A14 I/O1 - I/O8 CE
WE OE VCC VSS
A13
WE
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground
Vcc A14 A12 A7 A6 A5 A4 A3
UT62256C
21 20 19 18 17 16 15
STSOP
____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +7.0 0 to +70 -65 to +150 1 50 260 UNIT V J J W mA J
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec)
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write
Note: H = VIH, L=VIL, X = Don't care.
CE H L L L
OE X H L X
WE X H H L
I/O OPERATION High - Z High - Z DOUT DIN
SUPPLY CURRENT ISB, ISB1 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
DC ELECTRICAL CHARACTERISTICS (VCC = 5V10%, TA = 0J
PARAMETER SYMBOL TEST CONDITION *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VSS O VIN O VCC Output Leakage ILO VSS O VI/O O VCC Current CE =VIH or OE = VIH or WE = VIL Output High Voltage VOH IOH= - 1mA Output Low Voltage VOL IOL= 4mA Operating Power ICC - 35 CE = VIL , Supply Current II/O = 0mA ,Cycle=Min. - 70 ICC1 CE = 0.2V; II/O = 0mA Tcycle other pins at 0.2V or =500ns Tcycle ICC2 VCC-0.2V =1s normal Standby Power ISB =VIH CE Supply Current ISB1 CE U VCC-0.2V ISB -L/-LL CE =VIH ISB1 CE U VCC-0.2V -L -LL Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. 4. ISB1=20A for special requirement. MIN. 2.2 - 0.5 -1 -1
to 70J ) TYP. -
MAX. VCC+0.5 0.8 1 1
UNIT V V A A
2.4 -
40 30 1 0.3 2 1
0.4 50 40 20 10 10 5 3 100 50 4 20*
V V mA mA mA mA mA mA mA A A
____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25J , f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 100pF, IOH/IOL = -1mA/4mA to 70J )
AC ELECTRICAL CHARACTERISTICS (VCC = 5V10% , TA = 0J
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL UT62256C-35
MIN. MAX.
UT62256C-70
MIN. MAX.
UNIT
tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH
35 10 5 5
35 35 25 25 25 -
70 10 5 5
70 70 35 35 35 -
ns ns ns ns ns ns ns ns ns
SYMBOL
UT62256C-35
MIN. MAX.
UT62256C-70
MIN. MAX.
UNIT
tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
35 30 30 0 25 0 20 0 5 -
15
70 60 60 0 50 0 30 0 5 -
25
ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA tOH
Dout Previous data valid Data Valid
tOH
READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5)
tRC
Address
tAA
CE
tACE
OE
tOE tCLZ tOLZ
Dout High-Z Data Valid
tCHZ tOHZ tOH
High-Z
Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low. 3.Address must be valid prior to or coincident with CE =low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measuredO 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.3 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
tWC
Address
tAW
CE
tCW tAS
WE
tWP
tWR
tWHZ
Dout (4)
High-Z
tOW
(4)
tDW
Din
tDH
Data Valid
WRITE CYCLE 2 ( CE Controlled) (1,2,5,6)
tWC
A ddress
tAW
CE
tAS tCW tWP
tWR
WE
tWHZ
D out (4) H igh-Z
tDW
D in D ata V alid
tDH
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3
Notes : 1. WE , CE must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE .
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured O 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = 0J
PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE U VCC-0.2V IDR Vcc=3V tCDR tR CE U VCC-0.2V See Data Retention Waveforms (below)
to 70J
) MIN. 2.0 TYP. 1 0.5 MAX. 5.5 50 10 UNIT V A A ns ns
-L - LL
0 tRC*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE controlled)
VDR U VCC Vcc(min.)
2V Vcc(min.)
tCDR
CE VIH CE U VCC-0.2V
tR
VIH
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
SYMBOL
A1 A2 B c D E e eB L c
INCH(BASE) 0.010(MIN) 0.150O 0.001 0.018O 0.005 0.010O 0.004 1.460O 0.005 0.600O 0.010 0.100 (TYP) 0.640O 0.03 0.130O 0.010 o o 0 ~15
MM(REF) 0.254(MIN) 3.810O 0.254 0.457O 0.127 0.254O 0.102 37.084O 0.127 15.240O 0.254 2.540(TYP) 16.256O 0.762 3.302O 0.254 o o 0 ~15
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3 28 pin 330 mil SOP Package Outline Dimension
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
UNIT
SYMBOL
A A1 A2 b c D E E1 e L L1 S y c
INCH(BASE) 0.112 (MAX) 0.004(MIN) 0.098O 0.005 0.016 (TYP) 0.010 (TYP) 0.713O 0.005 0.331O 0.005 0.465O 0.012 0.050 (TYP) 0.0404O 0.008 0.067O 0.008 0.047 (MAX) 0.003(MAX) o o 0 a 10
MM(REF) 2.845 (MAX) 0.102(MIN) 2.489O 0.127 0.406(TYP) 0.254(TYP) 18.110O 0.127 8.407O 0.127 11.811O 0.305 1.270(TYP) 1.0255O 0.203 1.702 O 0.203 1.194 (MAX) 0.076(MAX) o o 0 a 10
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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UTRON
Rev. 1.3 28 pin 8x13.4mm STSOP Package Outline Dimension
HD
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
c L
1
28
e 14 15
"A"
D Seating Plane
E
y
14
15
A
A2 c
0 A1 SEATING PLANE
1
28
"A" DATAIL VIEW
L1
UNIT SYMBOL A A1 A2 D E e HD L1 y K
INCH(BASE) 0.047 (MAX) 0.004 O 0.002 0.039 O 0.002 0.465 O 0.004 0.315 O 0.004 0.022 (TYP) 0.528 O 0.008 0.0315 O 0.004 0.003 (MAX) o o 0 a 5
MM(REF) 1.20 (MAX) 0.10 O 0.05 1.00 O 0.05 11.800 O 0.100 8.000 O 0.100 0.55 (TYP) 13.40 O 0.20. 0.80 O 0.10 0.076 (MAX) o o 0 a 5
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
9
UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
PART NO. UT62256CPC-70 UT62256CPC-70L UT62256CPC-70LL UT62256CSC-35 UT62256CSC-35L UT62256CSC-35LL UT62256CSC-70 UT62256CSC-70L UT62256CSC-70LL UT62256CLS-35 UT62256CLS-35L UT62256CLS-35LL UT62256CLS-70 UT62256CLS-70L UT62256CLS-70LL ACCESS TIME (ns) 70 70 70 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) typ. 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A PACKAGE 28PIN PDIP 28PIN PDIP 28PIN PDIP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP
ORDERING INFORMATION (for lead free product)
PART NO. UT62256CPCL-70 UT62256CPCL-70L UT62256CPCL-70LL UT62256CSCL-35 UT62256CSCL-35L UT62256CSCL-35LL UT62256CSCL-70 UT62256CSCL-70L UT62256CSCL-70LL UT62256CLSL-35 UT62256CLSL-35L UT62256CLSL-35LL UT62256CLSL-70 UT62256CLSL-70L UT62256CLSL-70LL ACCESS TIME (ns) 70 70 70 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) typ. 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A 0.3mA 2A 1A PACKAGE 28PIN PDIP 28PIN PDIP 28PIN PDIP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN SOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
10
UTRON
Rev. 1.3
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
_____________________________________________________________________________________________ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
11

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